1. Field of the Invention
The present invention generally relates to lithographic systems and methods of lithographic exposure.
2. Description of the Related Art
The term “patterning means” as will be employed herein should be broadly interpreted to refer to means that can be used to endow an incoming radiation beam with a patterned cross-section, corresponding to a pattern that is to be created in a target portion of the substrate. The term “light valve” may also be used in this context. Generally, the pattern will correspond to a particular functional layer in a device being created in the target portion, such as an integrated circuit or other device (see below). Examples of such patterning means include:                (a) a mask: the concept of a mask is well known in lithography, and it includes mask types such as binary, alternating phase-shift, and attenuated phase-shift, as well as various hybrid mask types. Placement of such a mask in the radiation beam causes selective transmission (in the case of a transmissive mask) or reflection (in the case of a reflective mask) of the radiation impinging on the mask, according to the pattern on the mask. In the case of a mask, the support structure will generally be a mask table, which ensures that the mask can be held at a desired position in the incoming radiation beam, and that it can be moved relative to the beam if so desired;        (b) a programmable mirror array: an example of such a device is a matrix-addressable surface having a viscoelastic control layer and a reflective surface. The basic principle behind such an apparatus is that (for example) addressed areas of the reflective surface reflect incident light as diffracted light, whereas unaddressed areas reflect incident light as undiffracted light. Using an appropriate filter, the said undiffracted light can be filtered out of the reflected beam, leaving only the diffracted light behind; in this manner, the beam becomes patterned according to the addressing pattern of the matrix-addressable surface. The required matrix addressing can be performed using suitable electronic means. More information on such mirror arrays can be gleaned, for example, from U.S. Pat. No. 5,296,891 and U.S. Pat. No. 5,523,193, which are incorporated herein by reference. In the case of a programmable mirror array, the said support structure may be embodied as a frame or table, for example, which may be fixed or movable as required; and        (c) a programmable LCD array: an example of such a construction is given in U.S. Pat. No. 5,229,872, which is incorporated herein by reference. As above, the support structure in this case may be embodied as a frame or table, for example, which may be fixed or movable as required.        
For purposes of simplicity, the rest of this text may, at certain locations, specifically direct itself to examples involving a mask and mask table; however, the general principles discussed in such instances should be seen in the broader context of the patterning means as set forth above. Also, the projection system may hereinafter be referred to as the “lens”; however, this term should be broadly interpreted as encompassing various types of projection system, including refractive optics, reflective optics, and catadioptric systems, for example. The radiation system may also include components operating according to any of these design types for directing, shaping or controlling the projection beam of radiation, and such components may also be referred to below, collectively or singularly, as a “lens”.
Lithographic exposure apparatuses can be used, for example, in the manufacture of integrated circuits (ICs). In such a case, the patterning means may generate a circuit pattern corresponding to an individual layer of the IC, and this pattern can be imaged onto a target portion (e.g. comprising one or more dies) on a substrate (silicon wafer) that has been coated with a layer of radiation-sensitive material (resist). In general, a single wafer will contain a whole network of adjacent target portions that are successively irradiated via the projection system, one at a time.
In current apparatuses, employing patterning by a mask on a mask table, a distinction can be made between two different types of machine. In one type of lithographic exposure apparatus, each target portion is irradiated by exposing the entire mask pattern onto the target portion in one go; such an apparatus is commonly referred to as a wafer stepper. In an alternative apparatus—commonly referred to as a step-and-scan apparatus—each target portion is irradiated by progressively scanning the mask pattern under the projection beam in a given reference direction (the “scanning” direction) while synchronously scanning the substrate table parallel or anti-parallel to this direction. Because, in general, the projection system will have a magnification factor M (generally <1), the speed V at which the substrate table is scanned will be a factor M times that at which the mask table is scanned. More information with regard to lithographic devices as here described can be gleaned, for example, from U.S. Pat. No. 6,046,792, incorporated herein by reference.
It is to be noted that the lithographic apparatus may also be of a type having two or more substrate tables (and/or two or more mask tables). In such “multiple stage” devices the additional tables may be used in parallel, or preparatory steps may be carried out on one or more tables while one or more other tables are being used for exposures. Twin stage lithographic apparatus are described, for example, in U.S. Pat. No. 5,969,441 and WO 98/40791, incorporated herein by reference.
Among other things, lithographic systems are used in the manufacture of integrated circuits (ICs). Such systems commonly employ a lithographic exposure apparatus and a wafer track apparatus. The lithographic exposure apparatus is configured to project or expose circuit pattern residing on a reticle (e.g., mask) onto a target field of a silicon wafer substrate layer via an irradiating projection beam. The projection beam may encompass different types of electromagnetic radiation including, but not limited to, ultraviolet radiation (UV) and extreme ultra-violet radiation (EUV), as well as particle beams, such as ion beams or electron beams.
Generally, the silicon wafer layer is previously coated with radiation-sensitive material (e.g., resist) that interacts with the impinging projection beam to replicate the profile and features of the mask circuit pattern onto the wafer substrate target fields. In general, a single wafer layer will contain a entire network of adjacent target fields that are successively irradiated.
Current lithographic exposure apparatuses fall into two general categories: stepper tools and step-and-scan tools. In steppers, each target portion is irradiated by exposing the entire mask pattern onto the target portion at once. In step-and-scan tools, each target portion is irradiated by progressively scanning the mask circuit pattern under the projection beam in a given reference direction while synchronously scanning the substrate.
Irrespective of the tool used, the substrate may be subjected to a variety of processes before the exposure process. For example, as indicated above, the substrate will generally be treated with resist before exposure. Also, prior to exposure, the substrate may be subjected to cleaning, etching, ion implantation (e.g., doping), metallization, oxidation, chemo-mechanical polishing, priming, resist coating, soft bake processes, and measurement processes.
The substrate may also be subjected to a host of post-exposure processes, such as, for example, post exposure bake (PEB), development, hard bake, etching, ion implantation (e.g., doping), metallization, oxidation, chemo-mechanical polishing, cleaning, and measurement processes. And, if several layers are required, which is usually the case, the entire procedure, or variants thereof, will have to be repeated for each new layer.
These pre- and post-exposure processes are performed by stations or modules designed for their respective purposes. The substrate is subjected to these processing modules, as well as the lithographic exposure apparatus, in a pre-defined sequence. In this arrangement, the substrate wafers travel in a pre-specified processing path to get serviced by specific processing modules that can be tracked. The processing path can be monitored, recorded, controlled, and limited to specific paths.
As indicated in FIG. 1A, which schematically depicts lithographic system 100, wafer track apparatus 104 interconnects lithographic exposure apparatus 102 with a host of pre-processing modules 104, 106 and post exposure processing modules 104, 108. The pre- and post-exposure processing modules 104, 106, 108 can be apparatus that are external to the wafer track apparatus or modules that are internal to the wafer track apparatus. To accommodate the transfer of substrates between these processing steps the wafer track apparatus 104 may also include interface sections configured to transport the wafer substrates to and from lithographic exposure apparatus 102, pre-processing apparatus 106, post-processing apparatus 108, and transport the wafer substrates between the various processing modules internal to the wafer track apparatus 104. Pre-exposure processes external to the wafer track 106 may include, for example, cleaning, etching, ion implantation (e.g., doping), metallization, oxidation, chemo-mechanical polishing, and measurement apparatus. Pre-exposure process modules internal to the wafer track 104 may include, for example, wafer supply, resist coating, measurement, and soft bake modules. Post-processing modules internal to the wafer track 104 may include, for example, post-exposure bake (PEB), develop, hard bake, and measurement modules. Post-exposure processes external to the wafer track 108 may include, for example, cleaning, etching, ion implantation (e.g., doping), metallization, oxidation, chemo-mechanical polishing, and measurement apparatus.
Needless to say, it is important that the features and profile of the pattern exposed on the target field of the wafer substrate layer are replicated as accurately as possible. To this end, manufacturers normally specify key attributes, which can collectively be considered the critical dimension (CD) of the exposed pattern, in order to characterize the features and profile of the pattern and establish a benchmark level of quality and uniformity. The CD metric may include, for example, the gap between features, X and/or Y diameter of holes and/or posts, ellipticity of holes and/or posts, area of feature, feature sidewall angle, width at the top of a feature, width at the middle of a feature, width at the bottom of a feature, and line edge roughness.
There are, however, numerous activities during the lithographic fabrication process that affect the critical dimension uniformity (CDU) and compromise the quality of the exposed pattern. Indeed, the very pre- and post-exposure processes that service and treat the substrate wafers along the wafer track apparatus, such as, for example, the post exposure bake (PEB) processing module, contribute to variations in the CDU. Such variations may occur across a target field, across a wafer, and between wafers and ultimately result in loss of yield.